Recently, a trap type memory utilizing trap in insulating films instead of Floating Gate (FG) as electric charge accumulating layers of a FLASH memory draws attention.
FIG. 14 shows a plan view of a relevant trap type memory. As shown in FIG. 14, in the trap type memory, isolation regions 9 are disposed in predetermined regions of a semiconductor substrate so as to restrict active regions including source/drain regions 5. A plurality of gate electrodes 1 cross the active regions, and an electric charge accumulating film 7 is interposed between the gate electrode 1 and the active regions. In addition, the gate electrodes 1 are provided with gate sidewalls 2 and sidewalls 3. FIG. 15A is a cross sectional view taken along the line I-I′ shown in FIG. 14, and FIG. 15B is a cross sectional view taken along the line shown in FIG. 14. A first gate insulating film 6, the electric charge accumulating film 7, a second gate insulating film 8, the gate electrodes 1, the gate sidewalls 2, the sidewalls 3, and the source/drain regions 5 are formed on a silicon substrate 10 having the isolation regions 9. Herein, when the locality of accumulated electric charge is utilized, the regions of the electric charge accumulating film which are close to the source or the drain serve as memory nodes 11 and 12, respectively, and the write state of two bits can be realized per one cell. Therefore, the effective cell area per one bit can be reduced.
A general operation method of the trap type memory will be explained. In writing of electric charge, a positive voltage is applied to the gate electrode 1 and either one of the source/drain regions 5, thereby generating channel hot electrons and accumulating electrons in the electric charge accumulating film in the vicinity of an end of the drain. Erasing is carried out by applying a negative voltage to the gate electrode 1, applying a positive voltage to the erasing side of the source/drain regions 5, and injecting hot holes generated by interband tunneling to the electric charge accumulating layer. Reading of the write state is carried out by switching the source and the drain used in writing, and the write state is determined when the amount of the current that flows to the drain is equal to or less than a certain predetermined value when a positive voltage is applied to the gate electrode 1.
However, a first problematic point of the structure shown in FIG. 14 is that, since the two memory nodes 11 and 12 are connected to each other by the electric charge accumulating film 7 above a channel region, the accumulated electric charge of one of the memory nodes diffuses to the other node as writing/erasing of electric charge is repeated, thereby deteriorating rewriting endurance. In this case, stored information is changed, which causes an error, and the retention characteristic of written electric charge is also deteriorated. In addition, the electric charge that diffused to the vicinity of the center of the gate electrode cannot be erased, and erasure VT (threshold voltage) is increased.
Furthermore, after the 90 nm technology node, the retention characteristic of written electric charge cannot be ensured due to leakage of the accumulated electric charge; for this reason, it is difficult to thin the electric charge accumulating layer (the first gate insulating film 6, the electric charge accumulating film 7, and the second gate insulating film 8). More specifically, a second problematic point of the structure shown in FIG. 14 is that, since the electric charge accumulating layer cannot be thinned even when the gate length is shortened along with reduction of the cell area, short-channel characteristics cannot be maintained, and increase of the punch-through current and reduction of the ON/OFF ratio of a read current readily occur.
Mainly against the first problematic point, the cell structure shown in FIG. 16, in which two memory nodes are completely separated from each other, has been reported (see Non-Patent Literature 1). In this memory cell, the gate electrode 1 is formed on a third gate insulating film 13, which does not have the electric charge trap, the gate electrode 1 and the gate sidewalls 2 are sandwiched by second gate electrodes 14 formed on an electric charge accumulating gate insulating film comprising the first gate insulating film 6, the electric charge accumulating film 7, and the second gate insulating film 8, and these three gate electrodes are connected each other by a metal layer 15. The source/drain regions 5 are formed so as to sandwich the three gate electrodes. When this cell structure is used, the outflow of the accumulated electric charge of one of the memory nodes to the other one is eliminated since the memory nodes 11 and 12 are divided by the insulating film not containing the electric charge accumulating film.
Moreover, against the second problematic point, the cell structure shown in FIG. 17 in which a recessed portion is formed on a semiconductor substrate, and a channel is formed along sidewalls of the recessed portion has been proposed (for example, see Patent Literature 1). As shown in FIG. 17, the recessed portion is formed on the silicon substrate 10, and the source/drain regions 5 are formed at an upper portion and a bottom portion of the recessed portion. Furthermore, along the inner surface of the recessed portion, the first gate insulating film 6, the electric charge accumulating film 7, the second gate insulating film 8, and the gate electrode 1 are formed. In this structure, when the depth of the recessed portion is increased, the gate length can be increased effectively, the punch-through current and the read current can be suppressed, and the ON/OFF ratio can be improved.    Non-Patent Literature 1: 2005 Symposium on VLSI Technology Digest of Technical Paper, pp. 118-119    Patent Literature 1: Unexamined Japanese Patent Application KOKAI Publication No. 2003-332469